"This is one of the most modern books related on the noise coupling in modern Systems on Chip (SoC) design. It addresses the state of the art in the SoC design, covering a wide range of topics, including novel methodologies to identify noise coupling in silicon, interconnect and package helping locate potential noise issues, both before tape-out and even earlier in the design process. The coupling mechanisms are addressed from silicon device level to package and printed circuit board level and from the kHz region until the mm Wave frequency region. Special focus is provided in 3D integration and on Through Silicon Vias coupling mechanisms. In addition, emerging coupling topics are addressed such as thermal and optical interconnects performance, power delivery networks, electro-thermal considerations onto 3D integration and 3D floor planning based on thermal interactions.
A strong point of the book is that it has been written by a mixture of industrial experts and academic professors and researchers, providing in-depth theoretical background and discussion of the most important practical aspects. Therefore, this book will be a powerful tool for designers involved with high performance SoC design in both 2D and 3D ICs. Using this book, we able to utilize innovative coupling analysis flow and modeling, addressing all related needs, to analyze noise components, propagating not just through the substrate, but also through the parasitic interconnect and package and to identify substrate coupling noise contributors, levels and transfer functions."
- Costas Psychalinos, University of Patras, Greece

"This book addresses noise coupling in integrated systems, which is a topic mostly widespread in industrial developments...This book could contribute to developing a widespread culture about how to deal with noise coupling in modern integrated systems."
-Domenico Zito, Aarhus University, Denmark